Engineering Architect, Performance

Role overview

Investigate what processor performance measurements reveal about compilers, architecture, and real workloads, then turn those findings into improvements. You’ll lead performance analysis across AArch64 and RISC-V for AI and HPC applications, connecting benchmark results to issues such as scheduling, vectorization, pipeline behavior, or missing instructions. The findings will help guide compiler optimization, architecture proposals, and framework work.

Responsibilities

- Plan and run performance studies for AI inference, training, HPC benchmarks, and customer workloads. - Analyze results across C/C++, Fortran, and Julia applications, including latency, throughput, compute efficiency, and memory use. - Trace performance gaps to compiler decisions, generated code, processor behavior, or architecture limitations. - Use evidence to recommend compiler optimizations and potential instruction-set extensions. - Build and maintain benchmark infrastructure, using automation to support profiling and regression analysis. - Present actionable findings to compiler engineers and processor architects, and prepare competitive analyses.

Requirements

- Experience with performance analysis on AArch64, RISC-V, or comparable architectures. - Ability to interpret benchmark results in terms of compiler behavior and microarchitecture. - Familiarity with compiler technologies such as GCC, LLVM, or MLIR. - Knowledge of AI or HPC performance measures, including inference latency, training throughput, FLOPS, and memory bandwidth. - Strong scripting and automation skills for building analysis infrastructure. - Clear communication skills and the ability to support conclusions with data.

Nice to have

- Experience evaluating whether proposed instruction-set extensions improve AI and HPC workloads. - Background spanning compiler optimization and microarchitectural analysis. - Performance work across multiple language ecosystems, particularly Fortran and Julia.