Physical Design Engineer - Synth, Senior

Role overview

Own synthesis and timing convergence for key chip partitions, turning RTL into netlists ready for physical implementation. This hands-on senior role also develops synthesis methods and constraints, improves implementation quality, and connects architecture and RTL teams with verification and backend implementation partners.

Responsibilities

- Run synthesis for assigned partitions and subsystems, delivering implementation-ready netlists on schedule. - Improve synthesis flows, including timing budgets, constraint development, quality-of-results optimization, incremental synthesis, and hierarchical implementation. - Establish and apply signoff criteria for synthesis deliverables. - Develop and maintain SDC constraints, clock definitions, false and multicycle paths, generated clocks, and multi-mode, multi-corner environments. - Monitor and improve synthesis quality metrics while coordinating with RTL designers and implementation partners.

Requirements

The available source lists the role’s overview and the start of its responsibilities, but does not provide the specific required qualifications. No experience threshold, degree, or tool requirement can therefore be stated reliably.

Benefits and work setup

The source describes a remote-first setup with a company-provided computer and home-office equipment. Listed benefits include company-paid medical, dental, and vision coverage, life and disability coverage, supplemental insurance options, unlimited paid time off, 13 paid holidays, equity, and a 401(k) match. Applicants must already be authorized to work in the U.S.; new visa sponsorship is unavailable, though eligible H-1B transfers may be supported.