ASIC Physical Design Engineer, Senior

Role overview

Own physical implementation work for assigned blocks of advanced AI accelerator ASICs, helping take designs from early floorplanning through tapeout. The role focuses on achieving signoff-quality power, performance, and area results while contributing to implementation methods for complex, multi-block chips.

Responsibilities - Support floorplanning, macro placement, power planning, and bump planning. - Run clock tree synthesis, place and route, and routing optimization through timing closure. - Resolve signal integrity, IR/EM, congestion, DRC, LVS, and other signoff issues; implement ECOs and metal fill. - Contribute to power-grid methods, congestion analysis, wire estimation, and hierarchical implementation strategies. - Coordinate implementation deliverables with RTL, synthesis, DFT, package, and backend design partners. - Support physical-design tapeout signoff for owned blocks.

Requirements - Hands-on experience implementing ASIC blocks with Innovus-based flows. - Practical familiarity with physical-design and signoff tools such as ICC2, Tempus, PrimeTime, Voltus, RedHawk, and Calibre. - Ability to close designs across timing, power, area, congestion, DRC, LVS, EM, and IR constraints. - Experience contributing to physical implementation from floorplanning through tapeout. - Ability to collaborate across design and implementation teams on complex chip work.

Benefits and work setup - Remote-first work, with a company-provided computer and home-office setup. - Company-paid medical, dental, vision, life, and disability coverage; additional supplemental coverage is available. - Unlimited paid time off, 13 paid holidays, competitive salary and equity, and a 401(k) with company match. - Applicants must already be authorized to work in the U.S.; new visa sponsorship is unavailable, though eligible H-1B transfers may be supported.