ASIC Physical Design Engineer - Power, Senior

Role overview Drive power estimation, optimization, and verification for chip blocks and subsystems in an AI accelerator program. You will contribute to chip-level power strategy and improve analysis methods across the development lifecycle, from early architectural estimates through RTL and gate-level analysis and silicon validation.

Responsibilities - Own power approaches for assigned blocks, covering dynamic and leakage power as well as clock, memory, interconnect, idle, and peak power. - Build and maintain power models from early design stages through RTL and gate-level implementation. - Analyze vector-based and activity-driven power data against representative workload behavior. - Apply optimization methods such as clock gating, operand isolation, power gating, voltage islands, and multi-threshold cells. - Identify opportunities to reduce memory, pipeline, switching, and data-movement power, and provide actionable feedback to RTL teams. - Work with backend teams on power integrity, including IR-drop analysis and related implementation concerns.

Requirements - Senior-level experience in physical design power analysis, optimization, or verification for ASICs. - Ability to model and analyze power across architectural, RTL, and gate-level stages. - Practical experience with low-power design techniques and activity-based analysis. - Understanding of power integrity and collaboration with backend implementation teams. - Clear communication skills for turning analysis into design recommendations.

Benefits and work setup Remote-first work includes a company-provided computer and home-office setup. Benefits include fully paid medical, dental, and vision coverage for employees and dependents, life and disability coverage, optional supplemental insurance, unlimited paid time off, 13 company holidays, salary and equity, and a matching 401(k). Applicants need current U.S. work authorization; eligible H-1B transfers may be facilitated, but new sponsorship is unavailable.