ASIC Physical Design Engineer - DFT, Senior

Role overview Lead design-for-test implementation for custom AI accelerator chips, owning the work from DFT architecture through tapeout and initial silicon bring-up. This is a hands-on engineering role spanning RTL, synthesis, test flows, pre-silicon validation, and coordination with backend implementation teams.

Responsibilities - Design and implement scan, compression, ATPG, memory BIST, boundary-scan, IJTAG, and debug or observability features. - Integrate DFT logic into internal RTL and assess test capabilities in third-party IP. - Develop verification plans and validate DFT behavior through simulation and gate-level checks. - Plan stuck-at, transition, cell-aware, and power-aware ATPG strategies and meet test coverage goals before tapeout. - Work with physical design teams on scan-chain partitioning, compression, test clocks, and physical implementation. - Support silicon test and bring-up, investigating issues and improving test readiness.

Requirements - Significant hands-on experience implementing DFT for complex ASICs or SoCs. - Practical knowledge of scan insertion, ATPG, memory BIST, boundary scan, and IJTAG. - Experience working with RTL, synthesis, DFT tools, and simulation or gate-level verification. - Ability to collaborate with backend teams and carry design-for-test work through tapeout.

Benefits and work setup Remote-first work includes a company-provided computer and home-office setup. Benefits include fully paid medical, dental, and vision coverage for employees and dependents, life and disability coverage, optional supplemental insurance, unlimited paid time off, 13 company holidays, salary and equity, and a matching 401(k). Applicants need current U.S. work authorization; eligible H-1B transfers may be facilitated, but new sponsorship is unavailable.