ASIC Design Engineer, Senior

Role overview Own the design and delivery of critical blocks and subsystems for custom AI accelerator chips, from microarchitecture through RTL signoff. The role combines hands-on SystemVerilog development with technical leadership: setting design direction, coordinating with verification and physical design, improving implementation practices, and mentoring other engineers.

Responsibilities - Define and document microarchitectures for complex IP blocks and subsystems. - Develop parameterized SystemVerilog RTL with clear interfaces, power and clock intent, and embedded assertions. - Lead lint, clock and reset domain checks, DFT integration, and synthesis bring-up for assigned designs. - Track block-level power, performance, and area goals, and optimize the design to meet them. - Integrate interconnects, DMA, coherency logic, and high-speed memory interfaces; coordinate with IP vendors and internal teams. - Improve coding practices and reusable IP packaging, and mentor junior engineers.

Requirements - Strong ASIC design experience, including microarchitecture definition and production RTL implementation. - Proficiency in SystemVerilog and the design flow from concept through signoff. - Experience with design checks, synthesis, DFT coordination, and working with physical design teams on timing and floorplanning. - Familiarity with high-performance interconnect, DMA, coherency, or HBM/DDR integration. - Ability to lead technical work across teams and support less-experienced engineers.

Benefits and work setup The role offers a flexible work environment, salary and equity, and comprehensive benefits. The stated base salary range is $200,000–$300,000; final compensation may vary with experience and qualifications.