Engineering Architect, ISA & Co-Design

Role overview

Shape processor instruction-set extensions by connecting real AI and scientific-computing workloads with compiler and hardware design. You’ll identify where RISC-V falls short, define candidate instructions, demonstrate that compilers can use them, and assess their expected performance before hardware decisions are made. The role also includes technical engagement with architecture working groups and comparison of competing processor designs.

Responsibilities

- Analyze AI and HPC applications to identify performance limits that new instructions could address. - Specify extension encodings and semantics, including how they interact with existing architectural state and future compatibility. - Implement prototype support in GCC, LLVM, or MLIR to show that proposed instructions can be generated effectively. - Evaluate proposals using workloads such as inference, training, stencil computations, sparse linear algebra, and FFTs. - Use pre-silicon simulation and performance prediction to inform design decisions. - Present proposals to standards groups and compare architectures using AI and HPC benchmarks.

Requirements

- Deep understanding of at least one instruction set architecture at the microarchitectural level. - Experience analyzing AI or HPC workloads and relating application behavior to processor capabilities. - Ability to implement or assess compiler backend support for proposed instructions. - Understanding of how C/C++, Fortran, Julia, or similar languages use architecture features. - Familiarity with standards bodies or architecture working groups. - Strong technical communication skills for engaging with processor architects.

Nice to have

- Direct experience proposing or extending an ISA, including taking proposals through ratification or into silicon. - Contributions to RISC-V working groups. - Experience with Spike, QEMU, or custom pre-silicon simulators. - Perspective that connects workload, compiler, and microarchitecture trade-offs.