Performance Architect, CPU Cluster

Role overview

A hands-on CPU Cluster Performance Architect role focused on shaping the performance and scalability of next-generation multi-core CPU designs. The position centers on using performance models and simulation to study how cores, caches, coherent interconnects, and memory systems behave together, then turning those insights into architectural improvements. This remote opportunity based in North America is open to candidates at varying experience levels, with the specific level determined during the interview process.

Responsibilities

- Analyze and optimize CPU cluster performance, including cache hierarchies, interconnects, coherence protocols, and memory access behavior. - Build and use performance models and simulation environments such as Gem5 or equivalent to evaluate architectural concepts and surface performance opportunities. - Characterize real workloads to pinpoint bottlenecks related to cache misses, coherence traffic, memory bandwidth, latency, contention, and inter-core communication. - Drive architectural tradeoff studies spanning performance, scalability, bandwidth, latency, power consumption, and implementation complexity. - Partner with CPU, cache, interconnect, memory, software, and system architects to convert performance findings into concrete design decisions.

Requirements

- Strong foundation in CPU microarchitecture and performance, with a working understanding of how cores, caches, interconnects, and memory systems interact. - Hands-on experience using modeling, simulation, and workload analysis to investigate cluster-level performance bottlenecks and scaling challenges. - Comfort moving between detailed microarchitecture questions and broader system-level concerns involving latency, bandwidth, quality of service, utilization, and scalability. - Analytical mindset with the ability to distill large volumes of performance data into clear architectural recommendations. - Strong communication skills and a collaborative approach when working across architecture, RTL, compiler, software, and system teams.

Nice to have

- Familiarity with RISC-V instruction set architectures or other open instruction set ecosystems. - Exposure to chiplet-based system design and how compute, interconnect, and memory subsystems scale across dies.

Benefits and work setup

- Fully remote role based in North America. - Compensation for engineering roles spans roughly $100,000 to $500,000 including base and variable components; actual offers depend on experience, skills, education, and location. - Competitive benefits package. - Employment is contingent on eligibility to access U.S. export-controlled technology, which may require specific citizenship, permanent residency status, or prior federal license approval.