Front End Design Verification Engineer

Role overview A hardware engineering team developing next-generation high-performance RISC-V CPU cores is hiring a Front End Design Verification Engineer to verify the fetch unit. The work centers on the logic that keeps the processor fed with the right instructions at the right time, spanning instruction fetch and prediction through decode and dispatch. The role partners closely with CPU architects and RTL designers on an out-of-order CPU, with direct impact on performance and correctness.

Responsibilities - Develop verification strategies and sophisticated tests for the CPU front end - Debug complex failures and ensure correct behavior across a wide range of workloads and corner cases - Move between specifications, RTL, simulations, and waveforms to identify root causes - Build and use constrained-random testing, assertions, functional coverage, and testbenches - Collaborate with architects, RTL designers, and fellow verification engineers

Requirements - 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs - Strong SystemVerilog and UVM skills, including testbench development and functional coverage - Solid understanding of CPU architecture, with familiarity in pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution - Experience debugging RTL and simulation failures using waveforms and standard simulation tools - Strong programming skills in C/C++ and/or Python

Nice to have - Curiosity about high-performance CPUs and how microarchitectural decisions impact real-world processor performance - Experience verifying speculative execution, branches, redirects, exceptions, and pipeline flushes - Comfort working across architecture, RTL, DV, and software teams

Benefits and work setup - Remote position based in North America or Spain - Candidates at various experience levels are welcomed; level is assessed during the interview process - Compensation ranges from $100k to $500k including base and variable compensation targets, varying with experience, skills, education, background, and location