Architecture & Performance Modeling Engineer, AI Inference Silicon (Senior / Principal)

Role overview Shape the architecture of next-generation accelerators built for AI inference by turning design questions into quantified tradeoffs and recommendations. You will work with chip architects before RTL is available, using analytical models and internal simulators to explore options quickly, then refining and validating the models as designs mature. The role includes primary modeling responsibility for a future chip as well as contributions to shared modeling tools.

Responsibilities - Translate architectural questions into focused studies with explicit assumptions, alternatives, measurements, and recommendations. - Compare options for compute engines, memory capacity and bandwidth, dataflow, DMA, command processing, and on-chip and chip-to-chip communication. - Evaluate representative inference workloads across prefill and decode, batch sizes, context lengths, and dense and mixture-of-experts models. - Identify performance bottlenecks and sensitivities, and explain the implications of architectural choices. - Recommend design changes within system, power, area, and implementation constraints. - Refine and validate models as the architecture develops, and contribute to the shared modeling framework.

Requirements The available source describes the role and its modeling work but does not include enough of the qualifications section to state specific required experience or credentials.

Benefits and work setup The source describes a remote-first setup with a company-provided computer and home office equipment. Listed benefits include company-paid medical, dental, and vision coverage for employees and dependents; life and disability coverage; unlimited paid time off and 13 company holidays; salary, equity, and a 401(k) with matching. The role is open to people authorized to work in the United States; new visa sponsorship is unavailable, though eligible H-1B transfers may be supported.