DFT Engineer

Role overview A senior ASIC verification engineer position focused on the design-for-test (DFT) logic inside advanced silicon that powers large-scale AI data center clusters. The work centers on building robust verification environments, executing coverage-driven plans, and partnering closely with DFT designers and manufacturing engineers to deliver reliable, high-quality first silicon.

Responsibilities - Develop and maintain SystemVerilog/UVM verification environments for ASIC DFT logic. - Build and run coverage-driven verification plans tied to design specifications. - Use vendor DFT suites to generate and run pre-silicon tests for MBIST, scan fabric, and related structures. - Author directed tests for non-vendor DFT logic to exercise corner cases. - Support ATPG pattern validation and manufacturing reset sequencing at the SoC level. - Debug simulation results, perform root-cause analysis with DFT designers, and contribute to post-silicon bring-up.

Requirements - Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years in digital design verification, with at least 2 years in DFT verification. - Strong SystemVerilog and UVM (or comparable methodology) proficiency. - Experience with industry EDA simulators and DFT tools such as TestMax and Tessent. - Python scripting and automation skills. - Background verifying test sequences for high-speed PHYs including PCIe and 10G/40G/100G Ethernet.

Nice to have - SoC-level verification experience. - Familiarity with change-control systems such as Git.

Benefits and work setup - Target base salary of $160,000–$230,000 plus equity, benefits, and 401(k). - Mix of remote and on-site collaboration across U.S. and Canada locations within a venture-backed engineering culture.