Verification Engineer

Role overview Drive RTL verification for complex digital designs implemented across ASIC and FPGA platforms. The work spans verification planning, testbench development, simulation, coverage tracking, and issue resolution, partnering with RTL designers to establish confidence in design behavior before silicon delivery.

Responsibilities - Build and maintain verification environments using UVM or a comparable methodology. - Create coverage-driven plans from design specifications and develop directed and constrained-random tests to exercise expected behavior and corner cases. - Analyze simulation results, debug failures, and work with RTL engineers to find root causes. - Track functional and code coverage and drive verification activities toward closure. - Create reusable verification components and SystemVerilog Assertions. - Automate regressions and improve verification infrastructure with Python and scripting; contribute to design and verification reviews.

Requirements - Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related discipline. - At least seven years of digital design verification experience. - Strong hands-on experience with UVM or a similar verification methodology. - Proficiency in SystemVerilog, UVM, and Python. - Experience using industry-standard simulation tools such as Synopsys VCS, Questa, or Cadence Xcelium. - Solid digital design fundamentals and experience with bus or interconnect protocols such as AXI, AXI-S, and APB.

Nice to have - Experience verifying high-speed protocols such as PCIe, Ethernet, SPI, or I²C. - Familiarity with formal verification tools and methods, processor subsystems, or SoC-level designs. - Strong analytical, communication, and independent task-management skills.