RTL Design Engineer

Role overview

Design and deliver production-ready RTL for complex digital systems, translating architectural plans into scalable microarchitectures. The work spans the design lifecycle, with close attention to performance, power, and area and collaboration across architecture, verification, and physical design.

Responsibilities - Implement reusable RTL for digital subsystems in Verilog or SystemVerilog. - Turn architectural specifications into efficient, maintainable designs and document implementation choices. - Run linting and clock-domain crossing analysis, and prepare designs for synthesis. - Debug RTL during simulation and integration, and support early silicon investigation. - Partner with verification and backend teams on functional coverage and timing closure. - Contribute to design reviews and improve design methods, flows, and tools.

Requirements - Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field. - At least five years of RTL design experience. - Strong practical command of Verilog or SystemVerilog and sound digital design fundamentals. - Experience with simulation and debug tools such as VCS, Questa, Verdi, or DVE. - Familiarity with synthesis, timing, and physical design constraints.

Nice to have - Experience with AI or machine-learning accelerators, networking silicon, or SoCs. - Knowledge of low-power design, design-for-test, advanced process nodes, and scripting in Python or Tcl. - Experience using AI coding assistants in RTL work, with careful validation of generated code, or creating reusable design guidance.