Physical Design Engineer

Role overview Lead hands-on physical implementation of complex semiconductor blocks and subsystems from synthesized netlist through signoff. The role combines floorplanning, power and timing closure, physical verification, and top-level integration, while helping establish methods for meeting performance, power, area, and schedule goals.

Responsibilities - Develop floorplans that account for hierarchy, macros, interfaces, congestion, timing, power, and routability. - Drive placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and engineering change orders. - Own difficult setup, hold, congestion, and signal-integrity problems, and support timing convergence across blocks and at chip level. - Run or guide static timing analysis across modes and corners, including the effects of crosstalk and physical variation. - Develop power grids and support IR-drop, electromigration, and other power-integrity analysis. - Drive physical signoff checks such as DRC, LVS, antenna, density, and connectivity, while coordinating with RTL, DFT, verification, package, and SI/PI teams.

Requirements - Demonstrated ability to take complex physical designs from floorplanning through signoff. - Strong experience with physical implementation, timing analysis, and closure across multiple modes and corners. - Ability to debug issues spanning RTL, timing, physical implementation, and signoff. - Familiarity with implementation scripting or automation, including Tcl, Python, or similar languages. - Ability to work independently on complex problems and provide technical leadership across a team. - Comfortable moving between detailed implementation work and chip-level design considerations.

Nice to have - Experience with advanced process nodes or large, high-frequency, highly interconnected designs. - Background in hierarchical implementation, top-level integration, or physical design methodology development. - Work with package, SI/PI, power-delivery, multi-die, chiplet, or advanced packaging teams. - Familiarity with EDA tool evaluation and optimization, or experience in an early-stage semiconductor environment.