Engineering Architect, Compilers

Role overview

Develop compiler capabilities for AI and high-performance computing workloads across AArch64 and RISC-V. The role focuses on ambitious optimization and code-generation work that connects compiler intermediate representations to processor behavior, including support for emerging instruction-set extensions. You’ll shape GCC, LLVM, and MLIR through implementation, performance investigation, and open-source collaboration.

Responsibilities

- Design and implement compiler optimizations, including cost models, vectorization strategies, and scheduling heuristics. - Build code generation for RISC-V extensions aimed at AI, matrix operations, and scientific workloads. - Investigate performance problems that span compiler representations, generated code, and hardware pipelines. - Improve compilation for workloads such as inference, simulations, and scientific computing. - Work across C/C++, Fortran, and emerging Julia or domain-specific language use cases. - Contribute work to open-source compiler communities and communicate results with hardware teams.

Requirements

- Deep practical experience with GCC, LLVM, or MLIR compiler internals. - Strong C or C++ programming skills and understanding of compiler optimization. - Knowledge of processor architecture and the relationship between generated code and hardware behavior. - Experience with vectorization, scheduling, or code generation for AI or HPC workloads. - Active participation in open-source compiler communities. - Ability to evaluate and steer AI-assisted development tools using sound compiler judgment.

Nice to have

- Upstream contributions to both GCC and LLVM, or substantial MLIR work. - Experience with RISC-V vector extensions or ARM SVE/SME. - Fortran optimization experience or familiarity with Julia compiler internals. - A record of delivering optimizations that required revisiting established compiler assumptions.

Benefits and work setup

- Full-time, remote role.