Engineering Architect, AI & HPC Compilation

Role overview Design compiler infrastructure that helps custom AI and high-performance computing hardware deliver on its intended performance. You’ll work across framework representations, compiler intermediate forms, runtime needs, and hardware constraints, building compilation paths for workloads that may target hardware still in simulation. The scope includes both AI workloads and scientific computing.

Responsibilities - Build MLIR-based pipelines that translate framework-level representations into code for custom AI and HPC silicon. - Develop graph-lowering strategies and kernel optimizations to improve the fit between workloads and hardware capabilities. - Collaborate with instruction-set designers to evaluate whether proposed extensions can be compiled and effectively used. - Create compiler infrastructure for matrix operations, custom instructions, and non-standard data types. - Connect high-level optimization with LLVM and hardware-specific code generation. - Contribute to compiler community work through technical contributions, talks, or working groups.

Requirements - Strong experience at the intersection of compiler infrastructure, AI or HPC workloads, and hardware architecture. - Ability to build compilation pipelines and optimize performance beyond functional correctness. - Familiarity with MLIR and LLVM compiler technologies. - Ability to reason about hardware-specific constraints and their effects on generated code.

Nice to have - Experience compiling for custom or pre-silicon hardware. - Knowledge of quantization, sparsity, mixed precision, or HPC optimizations such as stencil computations, FFTs, and sparse linear algebra. - Familiarity with Julia compiler internals or with Flang or gfortran for performance-critical HPC code.

Benefits and work setup The position is full-time and remote.