Senior RTL Design Engineer, Processor Pipelines

Role overview Lead microarchitecture and RTL for major processor pipeline blocks, building the control needed to integrate unconventional execution units while meeting performance goals. This founding-level role has influence over architectural choices that remain open and requires close coordination with arithmetic, memory, verification, and software colleagues.

Responsibilities - Own pipeline block microarchitecture and RTL from specification through timing closure. - Design issue policy, hazard detection, forwarding, exception handling, and flush behavior around the execution units. - Evaluate architectural choices, document the reasoning, and make underlying assumptions explicit. - Take designs through synthesis and timing analysis, revising them when results expose problems. - Develop verification collateral alongside the RTL. - Coordinate interfaces and requirements with arithmetic, memory, software, and verification teams.

Requirements - Experience taking complex pipeline RTL from specification through tape-out, including learning from silicon results. - Deep SystemVerilog expertise and strong judgment about pipeline microarchitecture, hazards, and critical paths. - Fluency with synthesis and timing analysis, with readiness to change designs based on results. - Ability to work without a large supporting infrastructure team and contribute across adjacent areas. - Ability to explain microarchitectural reasoning to colleagues outside hardware design.

Benefits and work setup The role is remote within the United States, with several hours of daily overlap with Pacific time. Remote employees should expect about one week per month on site during the first year; travel and standard accommodation are covered. Relocation support may be available. The position is exempt and includes paid time off, access to available health plans and retirement benefits, and a possible equity opportunity during negotiation. Early work centers on owning a major pipeline block through synthesis and timing.