RTL Design Engineer

Role overview Take ownership of real processor pipeline blocks, developing RTL from microarchitecture through timing with guidance and design review from experienced colleagues. The role is intended for an engineer building production hardware experience while contributing across design, verification, and implementation in a small collaborative team.

Responsibilities - Develop SystemVerilog RTL for pipeline blocks, from microarchitectural decisions through timing closure. - Write verification collateral for the hardware you build. - Run synthesis and timing analysis on your blocks and use the results to improve them. - Contribute to other areas of the design as priorities shift. - Ask questions that surface unclear assumptions in your own work and the wider design.

Requirements - At least two years of SystemVerilog RTL experience in production or advanced R&D, or a strong graduate record that includes real tape-out involvement. - Solid digital design fundamentals, including pipelining, timing, clock domains, and synthesis behavior. - Scripting ability to create or adapt tools that support your work. - Willingness to raise uncertainty early and seek clarification. - Ability to use AI tools thoughtfully and check generated output for correctness.

Nice to have - Tape-out experience at any scale. - Familiarity with formal methods, assertion-based verification, or UVM. - Computer architecture coursework or projects beyond introductory material. - Clear communication and willingness to explain designs and ask others to explain theirs.

Benefits and work setup The role is remote within the United States, with several hours of daily overlap with Pacific time. Remote employees should expect about one week per month on site during the first year; travel and standard accommodation are covered. Relocation support may be available. The position is exempt and includes paid time off, access to available health plans and retirement benefits, and a possible equity opportunity during negotiation. Initial work includes owning a small but real block through timing, with support and review.